A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...
Aristides Efthymiou, Christos P. Sotiriou, Douglas...
Evaluation of incomplete algorithms that solve SAT requires to generate hard satisfiable instances. For that purpose, the kSAT uniform random generation is not usable. The other g...
Software that has been well tested and analyzed may fail unpredictably when a certain combination of conditions occurs. In Bounded Exhaustive Testing (BET) all combinations are te...
R. Barzin, S. Fukushima, William E. Howden, S. Sha...
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...