In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
A mathematical formula containing one or more free variables is "general" in the sense that it represents the solution to all instances of a problem (instead of just the...
John R. Koza, Martin A. Keane, Jessen Yu, William ...
This work discusses the use of an Evolvable Hardware (EHW) platform in the synthesis of analog electronic circuits for Fuzzy Logic Controllers. A Fuzzy Logic Controller (FLC) is d...
A subthreshold-leakage suppressed switched capacitor (SC) circuit based on super cut-off CMOS (SCCMOS) scheme is introduced. This scheme realizes low-voltage SC circuits using low...
K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, ...
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...