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» Synthesis of networks on chips for 3D systems on chips
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LPNMR
2009
Springer
14 years 3 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
IWANN
2007
Springer
14 years 2 months ago
Integration of Wind Sensors and Analogue VLSI for an Insect-Inspired Robot
We have designed an adaptive analogue VLSI neuromorphic chip that will be used to interface MEM wind sensors to an insectinspired robot. The main chip components are a sensory inte...
Y. Zhang, A. Hamilton, R. Cheung, B. Webb, P. Argy...
CF
2007
ACM
14 years 21 days ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
14 years 3 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
CODES
2007
IEEE
14 years 3 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens