419 search results - page 40 / 84 » Synthesis of networks on chips for 3D systems on chips |
ISPD
2003
ACM
14 years 1 months ago
2003
ACM
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
ENTCS
2008
13 years 8 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
CASES
2004
ACM
14 years 2 months ago
2004
ACM
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and ar...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...