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» Synthesis of networks on chips for 3D systems on chips
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ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 3 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 1 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
WIS
2004
13 years 10 months ago
AuthenLink: A User-Centred Authentication System for a Secure Mobile Commerce
We envision an environment where humans communicate directly with computers without additional authentication inputs like passwords, passphrases, PINs (Personal Identification Num...
Christina Braz, Esma Aïmeur
CDES
2006
100views Hardware» more  CDES 2006»
13 years 10 months ago
Integrity and Integration Issues for Nano-Tube Based Interconnect Systems
: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
Tulin Mangir
GLVLSI
2009
IEEE
132views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Multicast routing with dynamic packet fragmentation
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper