419 search results - page 57 / 84 » Synthesis of networks on chips for 3D systems on chips |
DSN
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
FPL
2008
Springer
13 years 10 months ago
2008
Springer
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
MVA
1992
13 years 9 months ago
1992
This study reports on the performance of a Real-Time Vision System (RVS) and its use of an IMAP prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a ...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
—Efficient routing schemes are essential if Network on Chip (NoC) architectures are to be used for implementing multi-core systems for real-time multi-media applications. These s...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...