419 search results - page 71 / 84 » Synthesis of networks on chips for 3D systems on chips |
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
SLIP
2004
ACM
14 years 2 months ago
2004
ACM
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
FPL
2006
Springer
14 years 8 days ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
CASES
2005
ACM
13 years 10 months ago
2005
ACM
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...