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» Synthesis of networks on chips for 3D systems on chips
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CVIU
2010
115views more  CVIU 2010»
13 years 8 months ago
A modified model for the Lobula Giant Movement Detector and its FPGA implementation
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
ISQED
2006
IEEE
124views Hardware» more  ISQED 2006»
14 years 2 months ago
DFM Metrics for Standard Cells
Design for Manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. ...
Robert C. Aitken
ISPASS
2009
IEEE
14 years 3 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
14 years 3 months ago
Application-aware prioritization mechanisms for on-chip networks
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chi...
MMB
2010
Springer
194views Communications» more  MMB 2010»
14 years 1 months ago
Searching for Tight Performance Bounds in Feed-Forward Networks
Abstract. Computing tight performance bounds in feed-forward networks under general assumptions about arrival and server models has turned out to be a challenging problem. Recently...
Andreas Kiefer, Nicos Gollan, Jens B. Schmitt