277 search results - page 54 / 56 » Synthesis of quantum logic circuits |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
TCAD
2002
13 years 7 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...