30 search results - page 4 / 6 » Synthesis of system verilog assertions |
SPIN
2000
Springer
13 years 10 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
ACTA
2010
13 years 7 months ago
2010
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
CODES
2005
IEEE
14 years 21 days ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
SIGSOFT
2010
ACM
13 years 5 months ago
2010
ACM
We present a novel technique for synthesising behaviour models that works for an expressive subset of liveness properties and conforms to the foundational requirements engineering...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...