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» System Design Validation Using Formal Models
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SIGSOFT
2003
ACM
14 years 8 months ago
Behaviour model elaboration using partial labelled transition systems
State machine based formalisms such as labelled transition systems (LTS) are generally assumed to be complete descriptions m behaviour at some level of abstraction: if a labelled ...
Sebastián Uchitel, Jeff Kramer, Jeff Magee
IJSN
2008
147views more  IJSN 2008»
13 years 8 months ago
Formal modelling and analysis of XML firewall for service-oriented systems
: Firewalls have been designed as a major component to protect a network or a server from being attacked. However, due to their emphasis on packet filtering rather than verifying u...
Haiping Xu, Mihir M. Ayachit, Abhinay Reddyreddy
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
14 years 4 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 25 days ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
14 years 1 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt