10159 search results - page 74 / 2032 » System Design Validation Using Formal Models |
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the us...
ASYNC
2007
IEEE
14 years 1 days ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
FMCAD
2007
Springer
13 years 12 months ago
2007
Springer
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
FAC
2008
13 years 8 months ago
2008
This paper describes the Mondex case study with UML class diagrams and restricting OCL constraints. The constraints have been formulated either as OCL class invariants or as OCL pr...
DRR
2010
13 years 10 months ago
2010
In this paper we present an OCR validation module, implemented for the System for Preservation of Electronic Resources (SPER) developed at the U.S. National Library of Medicine.1 ...