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DSD
2007
IEEE
119views Hardware» more  DSD 2007»
15 years 10 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...
138
Voted
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
15 years 4 months ago
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...
Weixun Wang, Xiaoke Qin, Prabhat Mishra
CDC
2010
IEEE
116views Control Systems» more  CDC 2010»
14 years 11 months ago
High level model predictive control for plug-and-play process control with stability guaranty
In this paper a method for designing a stabilizing high level model predictive controller for a hierarchical plugand-play process is presented. achieved by abstracting the lower la...
Axel Gottlieb Michelsen, Jakob Stoustrup
175
Voted
LCPC
2005
Springer
15 years 10 months ago
Software Thread Level Speculation for the Java Language and Virtual Machine Environment
Thread level speculation (TLS) has shown great promise as a strategy for fine to medium grain automatic parallelisation, and in a hardware context techniques to ensure correct TLS...
Christopher J. F. Pickett, Clark Verbrugge
DATE
2005
IEEE
91views Hardware» more  DATE 2005»
15 years 10 months ago
Reliability-Centric High-Level Synthesis
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...