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ATS
2010
IEEE
239views Hardware» more  ATS 2010»
14 years 11 months ago
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
Michael A. Kochte, Christian G. Zoellin, Rafal Bar...
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
15 years 8 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
FPL
2004
Springer
205views Hardware» more  FPL 2004»
15 years 9 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
FTCS
1998
79views more  FTCS 1998»
15 years 5 months ago
Proving Correctness of a Controller Algorithm for the RAID Level 5 System
Most RAID controllers implemented in industry are complicated and di cult to reason about. This complexity has led to software and hardware systems that are di cult to debug and h...
Mandana Vaziri, Nancy A. Lynch, Jeannette M. Wing
164
Voted
SENSYS
2004
ACM
15 years 9 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...