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GLVLSI
2007
IEEE
211views VLSI» more  GLVLSI 2007»
15 years 8 months ago
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
15 years 8 months ago
Stochastic modeling and optimization for robust power management in a partially observable system
As the hardware and software complexity grows, it is unlikely for the power management hardware/software to have a full observation of the entire system status. In this paper, we ...
Qinru Qiu, Ying Tan, Qing Wu
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
15 years 6 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
198
Voted

Publication
351views
17 years 2 months ago
Synthesizable High Level Hardware Descriptions
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized ha...
Jennifer Gillenwater, Gregory Malecha, Cherif Sala...
CODES
2002
IEEE
15 years 7 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh