12333 search results - page 27 / 2467 » System Level Modelling for Hardware Software Systems |
DSD
2006
IEEE
14 years 3 months ago
2006
IEEE
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
WSC
2004
13 years 10 months ago
2004
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
IMCSIT
2010
13 years 6 months ago
2010
The deployment of IEC61850 standard in the world of substation automation system brings to the use of specific strategies for architecture testing. To validate IEC61850 architectur...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...