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» System Level Modelling for Hardware Software Systems
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DATE
2006
IEEE
119views Hardware» more  DATE 2006»
14 years 3 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
ICCAD
2001
IEEE
93views Hardware» more  ICCAD 2001»
14 years 6 months ago
Software-Assisted Cache Replacement Mechanisms for Embedded Systems
Prabhat Jain, Srinivas Devadas, Daniel W. Engels, ...
MEMOCODE
2010
IEEE
13 years 7 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
CODES
2006
IEEE
14 years 3 months ago
Accurate yet fast modeling of real-time communication
Accurate modeling of communication is a necessary part of system level design for real-time safety-critical applications. For efficient prediction of a system’s performance, Tra...
Gunar Schirner, Rainer Dömer
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 3 months ago
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
Divya Arora, Srivaths Ravi, Anand Raghunathan, Nir...