60 search results - page 10 / 12 » System level clock tree synthesis for power optimization |
ICCAD
2007
IEEE
13 years 8 months ago
2007
IEEE
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
WETICE
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—DHT systems are structured overlay networks capable of using P2P resources as a scalable platform for very large data storage applications. However, their efficiency ex...
DATE
2006
IEEE
14 years 22 days ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
DSD
2010
IEEE
13 years 4 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...