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» System level design, a VHDL based approach
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VTS
1999
IEEE
106views Hardware» more  VTS 1999»
15 years 10 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
DAC
2007
ACM
16 years 7 months ago
Parameterized Macromodeling for Analog System-Level Design Exploration
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
Jian Wang, Xin Li, Lawrence T. Pileggi
MIDDLEWARE
2007
Springer
16 years 1 days ago
Promoting levels of openness on component-based adaptable middleware
It is widely accepted that middleware is an important architectural element which facilitates the development of software systems. In this paper we propose a novel approach for de...
Tarcisio da Rocha, Anna-Brith Arntsen, Arne Ketil ...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
15 years 10 months ago
System Level Design Using C++
This paper discusses the use of C++ for the design of digital systems. The paper distinguishes a number of different approaches towards the use of programming languages for digita...
Diederik Verkest, Joachim Kunkel, Frank Schirrmeis...
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
15 years 10 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis