Sciweavers

5744 search results - page 34 / 1149
» System level design, a VHDL based approach
Sort
View
VTS
2000
IEEE
76views Hardware» more  VTS 2000»
15 years 10 months ago
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
Sule Ozev, Alex Orailoglu
DSD
2006
IEEE
110views Hardware» more  DSD 2006»
16 years 2 hour ago
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
Ines Viskic, Rainer Dömer
ICCV
2005
IEEE
16 years 7 months ago
A Shape-Based Segmentation Approach: An Improved Technique Using Level Sets
We propose a novel approach for shape-based segmentation based on a specially designed level set function format. This format permits us to better control the process of object re...
Hossam E. Abd El Munim, Aly A. Farag
CODES
2009
IEEE
15 years 10 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
DT
2000
162views more  DT 2000»
15 years 5 months ago
RT-Level ITC'99 Benchmarks and First ATPG Results
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...