5744 search results - page 73 / 1149 » System level design, a VHDL based approach |
151
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
160
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AGENTS
1997
Springer
15 years 10 months ago
1997
Springer
We have been developing Rogue, an architecture that integrates high-level planning with a low-level executing robotic agent. Rogue is designed as the oce gofer task planner for X...
150
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GECCO
2003
Springer
15 years 11 months ago
2003
Springer
Initial results have been achieved for automatic synthesis of MEMS system-level lumped parameter models using genetic programming and bond graphs. This paper first discusses the ne...
182
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ATS
2010
IEEE
15 years 1 months ago
2010
IEEE
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
193
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FPL
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...