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CODES
2007
IEEE
14 years 2 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
14 years 5 days ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
LCPC
2005
Springer
14 years 1 months ago
A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization
The goal of this work is a systematic approach to compiler optimization for simultaneously optimizing across multiple levels of the memory hierarchy. Our approach combines compiler...
Chun Chen, Jacqueline Chame, Mary W. Hall, Kristin...
IEEEPACT
2007
IEEE
14 years 2 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
PE
2010
Springer
175views Optimization» more  PE 2010»
13 years 3 months ago
Generalized ERSS tree model: Revisiting working sets
Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem. Existing characterization studi...
Ricardo Koller, Akshat Verma, Raju Rangaswami