78 search results - page 12 / 16 » System level power and performance modeling of GALS point-to... |
DATE
2010
IEEE
14 years 17 days ago
2010
IEEE
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
PVM
1997
Springer
13 years 11 months ago
1997
Springer
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
PPAM
2005
Springer
14 years 29 days ago
2005
Springer
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarant...
ICS
1992
Tsinghua U.
13 years 11 months ago
1992
Tsinghua U.
CODE 2.0 is a graphical parallel programming system that targets the three goals of ease of use, portability, and production of efficient parallel code. Ease of use is provided by...