897 search results - page 159 / 180 » System-Level Design for FPGAs |
SLIP
2003
ACM
14 years 4 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
DATE
2010
IEEE
14 years 4 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
Today's MPSoC synthesis and exploration design flows start abstract input specification model captured in a system level design language. Usually this model is created from a...
ACSD
2006
IEEE
14 years 26 days ago
2006
IEEE
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...