88 search results - page 13 / 18 » System-Level Modeling of Dynamically Reconfigurable Hardware... |
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
ESTIMEDIA
2003
Springer
14 years 21 days ago
2003
Springer
Current multimedia applications are characterized by highly dynamic and non-deterministic behavior as well as high-performance requirements. In addition, portable devices demand a...
DSD
2009
IEEE
13 years 5 months ago
2009
IEEE
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
DATE
2002
IEEE
14 years 13 days ago
2002
IEEE
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
RECONFIG
2009
IEEE
14 years 2 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...