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DAC
2007
ACM
14 years 8 months ago
Multi-Core Design Automation Challenges
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the k...
John A. Darringer
DAC
2006
ACM
14 years 8 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 8 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ASPLOS
2008
ACM
13 years 9 months ago
No "power" struggles: coordinated multi-level power management for the data center
Power delivery, electricity consumption, and heat management are becoming key challenges in data center environments. Several past solutions have individually evaluated different ...
Ramya Raghavendra, Parthasarathy Ranganathan, Vani...
EMSOFT
2008
Springer
13 years 9 months ago
Automatically transforming and relating Uppaal models of embedded systems
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
Timothy Bourke, Arcot Sowmya