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DATE
2006
IEEE
135views Hardware» more  DATE 2006»
14 years 1 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
DAC
1997
ACM
13 years 11 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
DAC
2000
ACM
14 years 8 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
RTAS
2009
IEEE
14 years 2 months ago
The System-Level Simplex Architecture for Improved Real-Time Embedded System Safety
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...
Stanley Bak, Deepti K. Chivukula, Olugbemiga Adeku...
ISVLSI
2003
IEEE
115views VLSI» more  ISVLSI 2003»
14 years 24 days ago
Getting High-Performance Silicon from System-Level Design
System-level design techniques promise a way to lessen the productivity gap between fabrication and design. Unfortunately, these techniques have been slow to catch on, in part bec...
W. Rhett Davis