121 search results - page 9 / 25 » System-level power optimization: techniques and tools |
DAC
2008
ACM
14 years 9 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
VALUETOOLS
2006
ACM
14 years 1 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
ARITH
2009
IEEE
14 years 2 months ago
2009
IEEE
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
ISCAS
1999
IEEE
14 years 8 days ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and evaluation of ...