82 search results - page 4 / 17 » SystemC transaction level models and RTL verification |
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
SIES
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
Since its first release the system level language SystemC had a significant impact on various areas in VLSI-CAD. One remarkable benefit of SystemC lies in the of abstraction le...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...