82 search results - page 5 / 17 » SystemC transaction level models and RTL verification |
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
We described an H.264 decoder implemented with our design methodology, in which a system function model of transaction level is first captured in SystemC and refined into RTL with ...
26
Voted
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze Vanill...
DATE
2005
IEEE
13 years 9 months ago
2005
IEEE
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Most of the challenges related to the development of multi-processor platforms for complex wireless and multimedia applications fall into the Electronic System Level (ESL) domain....