82 search results - page 6 / 17 » SystemC transaction level models and RTL verification |
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...