Sciweavers

414 search results - page 65 / 83
» Systems Architectures for Transactional Network Interface
Sort
View
ASPLOS
1991
ACM
13 years 11 months ago
LimitLESS Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
David Chaiken, John Kubiatowicz, Anant Agarwal
MOBICOM
2012
ACM
11 years 9 months ago
RadioJockey: mining program execution to optimize cellular radio usage
Many networked applications that run in the background on a mobile device incur significant energy drains when using the cellular radio interface for communication. This is mainl...
Pavan K. Athivarapu, Ranjita Bhagwan, Saikat Guha,...
DRM
2005
Springer
14 years 28 days ago
DRM interoperability analysis from the perspective of a layered framework
Interoperability is currently seen as one of the most significant problems facing the digital rights management (DRM) industry. In this paper we consider the problem of interoper...
Gregory L. Heileman, Pramod A. Jamkhedkar
EUROPAR
2001
Springer
13 years 12 months ago
VIA Communication Performance on a Gigabit Ethernet Cluster
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
Mark Baker, Paul A. Farrell, Hong Ong, Stephen L. ...
DATE
2010
IEEE
169views Hardware» more  DATE 2010»
14 years 14 days ago
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
Daniele Ludovici, Alessandro Strano, Georgi Nedelt...