119 search results - page 15 / 24 » Targeting Tiled Architectures in Design Exploration |
ERSA
2010
13 years 5 months ago
2010
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...
ERSA
2008
13 years 9 months ago
2008
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
FCCM
2002
IEEE
14 years 15 days ago
2002
IEEE
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...