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ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 9 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
RTSS
1995
IEEE
13 years 10 months ago
Dual Priority Scheduling
In this paper, we present a new strategy for providing flexibility in hard real-time systems. This approach, based on dual priorities, retains the offline guarantees afforded to...
Robert I. Davis, Andy J. Wellings
ICCAD
1997
IEEE
86views Hardware» more  ICCAD 1997»
13 years 11 months ago
Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems
- Task preemption is a critical enabling mechanism in multi-task VLSI systems. On preemption, data in the register les must be preserved in order for the task to be resumed. This e...
Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
ICRA
2008
IEEE
183views Robotics» more  ICRA 2008»
14 years 1 months ago
Hybrid image-plane/stereo (HIPS) for orientation control of manipulators
— Planetary exploration systems, operating under severe environmental and operating conditions, have thus far successfully employed carefully calibrated stereo cameras and manipu...
Kevin Nickels
RTDB
1996
131views more  RTDB 1996»
13 years 8 months ago
Value-cognizant Admission Control Strategies for Real-Time DBMS
We propose and evaluate an admission control paradigm for RTDBS, in which a transaction is submitted to the system as a pair of processes: a primary task, and a recovery block. Th...
Azer Bestavros, Sue Nagy