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» Task Selection for a Multiscalar Processor
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MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
14 years 27 days ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
14 years 7 days ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi
CASES
2006
ACM
13 years 11 months ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
CASES
2001
ACM
13 years 11 months ago
Storage allocation for embedded processors
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted...
Jan Sjödin, Carl von Platen
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
13 years 11 months ago
Optimal code generation for embedded memory non-homogeneous register architectures
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
Guido Araujo, Sharad Malik