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DATE
2007
IEEE
185views Hardware» more  DATE 2007»
15 years 10 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha
DSD
2003
IEEE
106views Hardware» more  DSD 2003»
15 years 9 months ago
Analytical Bounds on the Threads in IXP1200 Network Processor
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] ...
S. T. G. S. Ramakrishna, H. S. Jamadagni
ISCAS
2003
IEEE
156views Hardware» more  ISCAS 2003»
15 years 9 months ago
GNOMES: a testbed for low power heterogeneous wireless sensor networks
Continuing trends in sensor, semiconductor and communication systems technology (smaller, faster, cheaper) make feasible very dense networks of fixed and mobile wireless devices ...
Erik Welsh, Walt Fish, J. Patrick Frantz
ISCIS
2003
Springer
15 years 9 months ago
Design and Evaluation of a Source Routed Ad Hoc Network
Effects of network parameters on the performance of mobile ad hoc networks (MANETs) have been widely investigated. However, there are certain issues related to the hardware implem...
Faysal Basci, Hakan Terzioglu, Taskin Koçak
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
15 years 9 months ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens