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ASYNC
1997
IEEE
83views Hardware» more  ASYNC 1997»
15 years 8 months ago
Response Time Properties of Some Asynchronous Circuits
Wediscuss response timeproperties of linear arrays and tree-like arrays of cells with various handshake communication behaviours. The response times of a networkare the delays bet...
Jo C. Ebergen, Robert Berks
DAC
2007
ACM
16 years 5 months ago
Layered Switching for Networks on Chip
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
Zhonghai Lu, Ming Liu, Axel Jantsch
ICCD
2008
IEEE
160views Hardware» more  ICCD 2008»
16 years 1 months ago
Fast arbiters for on-chip network switches
— The need for efficient implementation of simple crossbar schedulers has increased in the recent years due to the advent of on-chip interconnection networks that require low la...
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Gal...
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
16 years 1 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
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ICCAD
2007
IEEE
148views Hardware» more  ICCAD 2007»
16 years 1 months ago
Fast exact Toffoli network synthesis of reversible logic
— The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic...
Robert Wille, Daniel Große