3340 search results - page 176 / 668 » Teaching networking hardware |
139
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ICCAD
2001
IEEE
16 years 1 months ago
2001
IEEE
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
129
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
—Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible lo...
136
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
148
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DDECS
2008
IEEE
15 years 11 months ago
2008
IEEE
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
105
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...