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DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 8 months ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...
DSN
2005
IEEE
15 years 10 months ago
Assured Reconfiguration of Fail-Stop Systems
Hardware dependability improvements have led to a situation in which it is sometimes unnecessary to employ extensive hardware replication to mask hardware faults. Expanding upon o...
Elisabeth A. Strunk, John C. Knight, M. Anthony Ai...
ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
14 years 8 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
SIGCOMM
2010
ACM
15 years 4 months ago
Detecting the performance impact of upgrades in large operational networks
Networks continue to change to support new applications, improve reliability and performance and reduce the operational cost. The changes are made to the network in the form of up...
Ajay Anil Mahimkar, Han Hee Song, Zihui Ge, Aman S...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 1 months ago
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems
Although several analytical models have been proposed in the literature for different interconnection networks with deterministic routing, very few of them have considered the eff...
Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad