A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Hardware dependability improvements have led to a situation in which it is sometimes unnecessary to employ extensive hardware replication to mask hardware faults. Expanding upon o...
Elisabeth A. Strunk, John C. Knight, M. Anthony Ai...
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Networks continue to change to support new applications, improve reliability and performance and reduce the operational cost. The changes are made to the network in the form of up...
Ajay Anil Mahimkar, Han Hee Song, Zihui Ge, Aman S...
Although several analytical models have been proposed in the literature for different interconnection networks with deterministic routing, very few of them have considered the eff...