3340 search results - page 226 / 668 » Teaching networking hardware |
149
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CEEMAS
2007
Springer
15 years 11 months ago
2007
Springer
We present a multi-agent system designed to detect malicious traffic in high-speed networks. In order to match the performance requirements related to the traffic volume, the net...
137
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
127
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ISCA
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with...
125
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— NnSP is a stream-based programmable and codelevel statically reconfigurable processor for realization of neural networks in embedded systems. NnSP is provided with a n...
128
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ISQED
2006
IEEE
15 years 10 months ago
2006
IEEE
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...