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» Techniques for Formal Verification of Digital Systems: A Sys...
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ISORC
2000
IEEE
13 years 11 months ago
Verification of UML-Based Real-Time System Designs by Means of cTLA
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
Günter Graw, Peter Herrmann, Heiko Krumm
ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
13 years 11 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
BIRTHDAY
2007
Springer
13 years 11 months ago
Automating Verification of Cooperation, Control, and Design in Traffic Applications
We present a verification methodology for cooperating traffic agents covering analysis of cooperation strategies, realization of strategies through control, and implementation of c...
Werner Damm, Alfred Mikschl, Jens Oehlerking, Erns...
POPL
2009
ACM
14 years 8 months ago
Verifying distributed systems: the operational approach
This work develops an integrated approach to the verification of behaviourally rich programs, founded directly on operational semantics. The power of the approach is demonstrated ...
Tom Ridge
ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella