66 search results - page 4 / 14 » Techniques for extracting instruction level parallelism on M... |
CGO
2005
IEEE
14 years 10 days ago
2005
IEEE
In this paper, we describe how to extend the concept of superword-level parallelization (SLP), used for multimedia extension architectures, so that it can be applied in the presen...
ICPP
2000
IEEE
13 years 11 months ago
2000
IEEE
Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level parallelism (ILP). An outcome of an instructio...
IFIPPACT
1994
13 years 8 months ago
1994
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope ...
ISCAPDCS
2003
13 years 8 months ago
2003
In modern computer systems loops present a great deal of opportunities for increasing Instruction Level and Thread Level Parallelism. Loop unrolling is a technique used to obtain ...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...