66 search results - page 5 / 14 » Techniques for extracting instruction level parallelism on M... |
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
LCTRTS
2007
Springer
14 years 3 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
HPCA
2002
IEEE
14 years 10 months ago
2002
IEEE
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
ISCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...