106 search results - page 4 / 22 » Techniques for improving the accuracy of geometric-programmi... |
DATE
2010
IEEE
14 years 16 days ago
2010
IEEE
Abstract—This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultr...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...