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DSD
2007
IEEE
132views Hardware» more  DSD 2007»
13 years 11 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
ENGL
2007
160views more  ENGL 2007»
13 years 7 months ago
Diagnosis and Classification of Epilepsy Risk Levels from EEG Signals Using Fuzzy Aggregation Techniques
— This paper is intended to compare the performance of four different types of fuzzy aggregation methods in classification of epilepsy risk levels from EEG Signal parameters. The...
R. Sukanesh, R. Harikumar
CASES
2007
ACM
13 years 11 months ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...
ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
14 years 10 days ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
ICCAD
2003
IEEE
111views Hardware» more  ICCAD 2003»
14 years 4 months ago
Formal Methods for Dynamic Power Management
Dynamic Power Management or DPM refers to the problem of judicious application of various low power techniques based on runtime conditions in an embedded system to minimize the to...
Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla