82 search results - page 14 / 17 » Techniques to Reduce Data Volume and Application Time for Tr... |
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
EUROPAR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
MM
2003
ACM
14 years 24 days ago
2003
ACM
The goal of tele-immersion has long been to enable people at remote locations to share a sense of presence. A tele-immersion system acquires the 3D representation of a collaborato...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
EUROGRAPHICS
2010
Eurographics
14 years 4 months ago
2010
Eurographics
Hierarchical culling is a key acceleration technique used to efficiently handle massive models for ray tracing, collision detection, etc. To support such hierarchical culling, bo...