138 search results - page 4 / 28 » Technology Mapping for Electrically Programmable Gate Arrays |
IJVR
2007
13 years 7 months ago
2007
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
VLSISP
2008
13 years 7 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...