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» Temporal Modeling of Software Test Coverage
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CODES
2004
IEEE
13 years 10 months ago
System-on-chip validation using UML and CWL
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo...
SIGSOFT
2006
ACM
14 years 7 months ago
SYNERGY: a new algorithm for property checking
We consider the problem if a given program satisfies a specified safety property. Interesting programs have infinite state spaces, with inputs ranging over infinite domains, and f...
Bhargav S. Gulavani, Thomas A. Henzinger, Yamini K...
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 4 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
ISSRE
2006
IEEE
14 years 1 months ago
Studying the Characteristics of a "Good" GUI Test Suite
The widespread deployment of graphical-user interfaces (GUIs) has increased the overall complexity of testing. A GUI test designer needs to perform the daunting task of adequately...
Qing Xie, Atif M. Memon
EMSOFT
2004
Springer
14 years 11 days ago
Scheduling within temporal partitions: response-time analysis and server design
As the bandwidth of CPUs and networks continues to grow, it becomes more attractive, for efficiency reasons, to share such resources among several applications with the minimum le...
Luís Almeida, Paulo Pedreiras