15 search results - page 2 / 3 » Test Compaction for Synchronous Sequential Circuits by Test ... |
DATE
1997
IEEE
14 years 24 days ago
1997
IEEE
VTS
1997
IEEE
14 years 23 days ago
1997
IEEE
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
EURODAC
1995
IEEE
14 years 3 days ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
1999
IEEE
14 years 27 days ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICCAD
1997
IEEE
14 years 23 days ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...