Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
An important number of studies have addressed the importance of models in software engineering, mainly in the design of robust software systems. Although models have been proven t...
In the foreseeable future, software testing will remain one of the best tools we have at our disposal to ensure software dependability. Empirical studies are crucial to software t...
The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all ...
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mik...